Branch Prediction of Conditional Nested Loops through an Address Queue

Multi-dimensional applications, such as image processing and seismic analysis, usually require the optimized performance obtained from instruction-level parallelism. The critical sections of such applications consist of nested loops with the possibility of embedded conditional branch instructions. Branch prediction techniques usually require extra hardware, redundancy or do not guarantee the prediction accuracy. This paper shows a new architecture design, able to handle the conditional branches found in nested loops with minimum extra hardware and one hundred percent prediction accuracy. Detailed examples demonstrate the effectiveness of the method.